Evidence used
- No CISA KEV confirmation is currently recorded.
- Exploitation requires an existing local or physical foothold with privileges.
- EPSS is 0.13% for the current model date.
BlackTreeCVE IntelligenceFull vulnerability report · 2026
CVE-2025-61972High confidence
AMD AMD EPYC™ 9004 Series Processors — Security-Sensitive Hardware Controls with Missing Lock Bit Protection
AMD · AMD EPYC™ 9004 Series Processors
8.5HighCVSS 4.0
Within 7 days
Patch availableHigh technical severity; prioritise exposed affected systems while verifying vendor guidance.
R
Open reassessment dashboard →Operational reassessment
Published severity in operational context
Published severityHigh→Operational priority:Medium, lowered one band.downgradedsince 14 May 2026
Compensating controls
- Validate the affected product branch and deploy the verified fixed release.
- Restrict local access and enforce least privilege on affected hosts.
- Monitor vendor guidance and exploitation sources for a material change.
Verification
- Confirm that the asset runs AMD AMD EPYC™ 9004 Series Processors and falls inside the recorded affected range.
- Verify the installed build against the product-specific fixed version after deployment.
- Validate exposure, authentication requirements and compensating controls in the actual environment.
- Reopen this reassessment when CVSS, KEV, EPSS, exploit evidence or remediation changes.
High technical severity; prioritise exposed affected systems while verifying vendor guidance.
Patch available01
What, why and how
Missing lock bit protection for NBIO registers could allow a local admin-privileged attacker to gain arbitrary System Management Network (SMN) access, potentially resulting in arbitrary code execution in AMD Secure Processor (ASP) and loss of the SEV-SNP guest's confidentiality and integrity.
What
Missing lock bit protection for NBIO registers could allow a local admin-privileged attacker to gain arbitrary System Management Network (SMN) access, potentially resulting in arbitrary code execution in AMD Secure Processor (ASP) and loss of the SEV-SNP guest's confidentiality and integrity.
Why
The product uses a register lock bit protection mechanism, but it does not ensure that the lock bit prevents modification of system registers or controls that perform changes to important hardware system configuration.
How
An attacker operating through local access may attempt exploitation with elevated privileges. If successful, the issue may execute code or commands in the affected security context.
What
Missing lock bit protection for NBIO registers could allow a local admin-privileged attacker to gain arbitrary System Management Network (SMN) access, potentially resulting in arbitrary code execution in AMD Secure Processor (ASP) and loss of the SEV-SNP guest's confidentiality and integrity.
Why
The product uses a register lock bit protection mechanism, but it does not ensure that the lock bit prevents modification of system registers or controls that perform changes to important hardware system configuration.
How
An attacker operating through local access may attempt exploitation with elevated privileges. If successful, the issue may execute code or commands in the affected security context.
02
Exploit reality and attack path
CVSS severity, EPSS forecast probability, public exploit material and CISA-confirmed exploitation are separate signals.
Observed exploitation No confirmed evidence
?
Confirmed exploitation and public exploit material are separate signals. Attacks can occur without public proof-of-concept or exploit code.No CISA KEV match was present at the last successful refresh. This means no confirmation from that source, not proof of no exploitation.
Public PoC / exploit material None recorded
?
Confirmed exploitation and public exploit material are separate signals. Attacks can occur without public proof-of-concept or exploit code.No exploit-tagged reference or CISA SSVC proof-of-concept state is currently recorded. Research may still exist outside the structured feeds.
- Likely attack path
- local access → Security-Sensitive Hardware Controls with Missing Lock Bit Protection → execute code or commands in the affected security context
- Attack surface
- Local
- Privileges required
- High: elevated access is required
- User interaction
- None
- Attack complexity
- High: exploitation depends on specific conditions
- Security boundary
- Not a CVSS 4.0 base metric
- Weakness
?
CWE means Common Weakness Enumeration: a standard category for the underlying weakness. - CWE-1233 ↗
CWE-1233: Security-Sensitive Hardware Controls with Missing Lock Bit Protection. The product uses a register lock bit protection mechanism, but it does not ensure that the lock bit prevents modification of system registers or controls that perform changes to important hardware system configuration.
- CVSS vector
?
CVSS means Common Vulnerability Scoring System. The vector records the metric values used to calculate technical severity. CVSS:4.0/AV:L/AC:H/AT:N/PR:H/UI:N/VC:H/VI:H/VA:N/SC:H/SI:H/SA:NCommon Vulnerability Scoring System 4.0: the compact vector below is decoded into plain language.
AVLocalAttack vector: The attacker needs local access to the vulnerable system.ACHighAttack complexity: Successful exploitation depends on specific conditions outside the attacker's direct control.ATNoneAttack requirements: No additional deployment or execution condition is required.PRHighPrivileges required: The attacker needs elevated or administrative privileges.UINoneUser interaction: No action by another user is required.VCHighVulnerable-system confidentiality: A successful attack can cause a major loss.VIHighVulnerable-system integrity: A successful attack can cause a major loss.VANoneVulnerable-system availability: No direct loss is represented by this metric.SCHighSubsequent-system confidentiality: A successful attack can cause a major loss.SIHighSubsequent-system integrity: A successful attack can cause a major loss.SANoneSubsequent-system availability: No direct loss is represented by this metric.- Post-exploitation / living off the land
- After compromise, an attacker may use built-in shells, scripting engines, scheduled tasks and native network utilities for discovery, persistence or movement. This is a plausible LoTL path, not evidence that it has occurred for every attack.
03
Patch and workaround
Operational remediation based on structured source evidence.
- Status
?
Patch availability is based on structured fixed-version fields and authoritative update references. If no fix is verified, check the vendor advisory before making a change. - Patch available
- Fixed
- AMD EPYC™ 9004 Series Processors: GenoaPI_1.0.0.H
- AMD EPYC™ 9005 Series Processors: TurinPI_1.0.0.8
- AMD EPYC™ 8004 Series Processors: GenoaPI_1.0.0.H
- AMD EPYC™ Embedded 9004 Series Processors (formerly codenamed "Genoa"): EmbGenoaPI-SP5 1.0.0.D
- AMD EPYC™ Embedded 9004 Series Processors (formerly codenamed "Bergamo"): EmbGenoaPI-SP5 1.0.0.D
- AMD EPYC™ Embedded 8004 Series Processors: EmbGenoaPI-SP5 1.0.0.D
- AMD EPYC™ Embedded 9005 Series Processors: EmbeddedTurinPI_SP5_1004
- Action
- Review the linked authoritative reference and apply the recorded fixed release appropriate to the affected product branch.
- Workaround
- No verified workaround is recorded. Limit untrusted access and use least privilege until authoritative guidance is available.
04
Evidence and provenance
Published 13 May 2026 · Last source change 14 May 2026, 03:56 UTC · CWE-1233 · Security-Sensitive Hardware Controls with Missing Lock Bit Protection
CVE recordCVE.org · 5.2
CVSS sourceCNA
EPSS source FIRST · tracked since 2026-08-14
?
The date BlackTree first stored a score for this CVE from the daily FIRST EPSS feed.European sourceENISA EUVD · EUVD-2025-209812
Product sourceCNA
Remediation sourceCVE/CNA references
CWE sourceCNA
NVD statusNVD awaiting enrichment
Missing structured fields: affected versions. Missing data is not evidence of low risk; review the primary advisory.
Material change intelligence
View recent updates ↗What changed after publication
No material field changes have been recorded since change tracking began. Routine source refreshes and cosmetic edits are intentionally excluded.
CVE published
Fixed release or patch reference recorded
Technical terms and abbreviations used in this report
- CVE
- Common Vulnerabilities and Exposures: the public identifier for one disclosed vulnerability.
- CVSS
- Common Vulnerability Scoring System: a technical severity framework; it is not patching priority by itself.
- EPSS
- Exploit Prediction Scoring System: FIRST's estimate of the probability that exploitation activity will be observed in the next 30 days; it is a forecast, not confirmation.
- CWE
- Common Weakness Enumeration: the standard category describing the underlying software or hardware weakness.
- CNA
- CVE Numbering Authority: an organisation authorised to assign and publish CVE records.
- CISA ADP
- Cybersecurity and Infrastructure Security Agency Authorized Data Publisher: structured enrichment added to a CVE record.
- NVD
- National Vulnerability Database: NIST's enrichment service for CVE records.
- CERT / CSIRT
- A computer security incident response team that publishes warnings or coordinates incident response.
- PoC
- Proof of concept: public material that demonstrates or helps reproduce exploitation.
- CSAF
- Common Security Advisory Framework: a machine-readable format for security advisories.
- LoTL
- Living off the land: abuse of legitimate tools or system functions during an attack.