Evidence used
- No CISA KEV confirmation is currently recorded.
- EPSS is 0.20% for the current model date.
BlackTreeCVE IntelligenceFull vulnerability report · 2025
CVE-2025-54520High confidence
Improper Protection Against Voltage and Clock Glitches in FPGA devices, could allow an attacker with physical access to undervolt the platform resulting in a loss of confidentiality
AMD · Kintex™ 7-Series FPGA
8.6HighCVSS 4.0
Within 7 days
Fix not verifiedHigh technical severity; prioritise exposed affected systems while verifying vendor guidance.
R
Open reassessment dashboard →Operational reassessment
Published severity in operational context
Published severityHigh→Operational priority:High, unchanged from published severity.unchanged
Compensating controls
- Restrict local access and enforce least privilege on affected hosts.
- Monitor vendor guidance and exploitation sources for a material change.
Verification
- Confirm that the asset runs AMD Kintex™ 7-Series FPGA and falls inside the recorded affected range.
- Recheck the vendor advisory before scheduling a change because no verified fixed version is currently retained.
- Validate exposure, authentication requirements and compensating controls in the actual environment.
- Reopen this reassessment when CVSS, KEV, EPSS, exploit evidence or remediation changes.
High technical severity; prioritise exposed affected systems while verifying vendor guidance.
Fix not verified01
What, why and how
Improper Protection Against Voltage and Clock Glitches in FPGA devices, could allow an attacker with physical access to undervolt the platform resulting in a loss of confidentiality.
What
Improper Protection Against Voltage and Clock Glitches in FPGA devices, could allow an attacker with physical access to undervolt the platform resulting in a loss of confidentiality.
Why
The device does not contain or contains incorrectly implemented circuitry or sensors to detect and mitigate voltage and clock glitches and protect sensitive information or software contained on the device.
How
An attacker operating through physical access may attempt exploitation without authentication or user interaction. If successful, the issue may cause the confidentiality, integrity or availability impact described by the vendor.
What
Improper Protection Against Voltage and Clock Glitches in FPGA devices, could allow an attacker with physical access to undervolt the platform resulting in a loss of confidentiality.
Why
The device does not contain or contains incorrectly implemented circuitry or sensors to detect and mitigate voltage and clock glitches and protect sensitive information or software contained on the device.
How
An attacker operating through physical access may attempt exploitation without authentication or user interaction. If successful, the issue may cause the confidentiality, integrity or availability impact described by the vendor.
02
Exploit reality and attack path
CVSS severity, EPSS forecast probability, public exploit material and CISA-confirmed exploitation are separate signals.
Observed exploitation No confirmed evidence
?
Confirmed exploitation and public exploit material are separate signals. Attacks can occur without public proof-of-concept or exploit code.No CISA KEV match was present at the last successful refresh. This means no confirmation from that source, not proof of no exploitation.
Public PoC / exploit material None recorded
?
Confirmed exploitation and public exploit material are separate signals. Attacks can occur without public proof-of-concept or exploit code.No exploit-tagged reference or CISA SSVC proof-of-concept state is currently recorded. Research may still exist outside the structured feeds.
- Likely attack path
- physical access → Improper Protection Against Voltage and Clock Glitches → cause the confidentiality, integrity or availability impact described by the vendor
- Attack surface
- Physical
- Privileges required
- None: unauthenticated exploitation is possible
- User interaction
- None
- Attack complexity
- Low: no specialised conditions are recorded
- Security boundary
- Not a CVSS 4.0 base metric
- Weakness
?
CWE means Common Weakness Enumeration: a standard category for the underlying weakness. - CWE-1247 ↗
CWE-1247: Improper Protection Against Voltage and Clock Glitches. The device does not contain or contains incorrectly implemented circuitry or sensors to detect and mitigate voltage and clock glitches and protect sensitive information or software contained on the device.
- CVSS vector
?
CVSS means Common Vulnerability Scoring System. The vector records the metric values used to calculate technical severity. CVSS:4.0/AV:P/AC:L/AT:N/PR:N/UI:N/VC:H/VI:H/VA:H/SC:H/SI:H/SA:HCommon Vulnerability Scoring System 4.0: the compact vector below is decoded into plain language.
AVPhysicalAttack vector: The attacker needs physical access to the vulnerable system.ACLowAttack complexity: No specialised conditions are required beyond attacker-controlled input.ATNoneAttack requirements: No additional deployment or execution condition is required.PRNonePrivileges required: The attacker does not need an account or existing privileges.UINoneUser interaction: No action by another user is required.VCHighVulnerable-system confidentiality: A successful attack can cause a major loss.VIHighVulnerable-system integrity: A successful attack can cause a major loss.VAHighVulnerable-system availability: A successful attack can cause a major loss.SCHighSubsequent-system confidentiality: A successful attack can cause a major loss.SIHighSubsequent-system integrity: A successful attack can cause a major loss.SAHighSubsequent-system availability: A successful attack can cause a major loss.- Post-exploitation / living off the land
- No specific living-off-the-land technique is confirmed in the structured sources. Monitor normal administration tools for activity inconsistent with the affected service's baseline.
03
Patch and workaround
Operational remediation based on structured source evidence.
- Status
?
Patch availability is based on structured fixed-version fields and authoritative update references. If no fix is verified, check the vendor advisory before making a change. - Fix not verified
- Affected
- Kintex™ 7-Series FPGA: Refer to AMD-SB-8018
- Artix™ 7-Series FPGA: Refer to AMD-SB-8018
- Fixed
- No fixed version is explicitly recorded in the structured CVE data.
- Action
- No verified patch reference is present in the current structured sources. Check the vendor advisory before making a change.
- Workaround
- No verified workaround is recorded. Limit untrusted access and use least privilege until authoritative guidance is available.
04
Evidence and provenance
Published 24 Sept 2025 · Last source change 25 Sept 2025, 13:48 UTC · CWE-1247 · Improper Protection Against Voltage and Clock Glitches
CVE recordCVE.org · 5.1
CVSS sourceCNA
EPSS source FIRST · tracked since 2026-08-14
?
The date BlackTree first stored a score for this CVE from the daily FIRST EPSS feed.European sourceENISA EUVD · EUVD-2025-31074
Product sourceCNA
Remediation sourceCVE/CNA references
CWE sourceCNA
NVD statusNVD not scheduled
Core structured fields are present and their contributing authorities are shown above.
Material change intelligence
View recent updates ↗What changed after publication
No material field changes have been recorded since change tracking began. Routine source refreshes and cosmetic edits are intentionally excluded.
Technical terms and abbreviations used in this report
- CVE
- Common Vulnerabilities and Exposures: the public identifier for one disclosed vulnerability.
- CVSS
- Common Vulnerability Scoring System: a technical severity framework; it is not patching priority by itself.
- EPSS
- Exploit Prediction Scoring System: FIRST's estimate of the probability that exploitation activity will be observed in the next 30 days; it is a forecast, not confirmation.
- CWE
- Common Weakness Enumeration: the standard category describing the underlying software or hardware weakness.
- CNA
- CVE Numbering Authority: an organisation authorised to assign and publish CVE records.
- CISA ADP
- Cybersecurity and Infrastructure Security Agency Authorized Data Publisher: structured enrichment added to a CVE record.
- NVD
- National Vulnerability Database: NIST's enrichment service for CVE records.
- CERT / CSIRT
- A computer security incident response team that publishes warnings or coordinates incident response.
- PoC
- Proof of concept: public material that demonstrates or helps reproduce exploitation.
- CSAF
- Common Security Advisory Framework: a machine-readable format for security advisories.
- LoTL
- Living off the land: abuse of legitimate tools or system functions during an attack.