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Full vulnerability report · 2026
CVE-2025-35979High confidence

n/a Intel(R) Processors — Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution

Unknown · Intel(R) Processors

6.8MediumCVSS 4.0
Recommended action
Patch only the product branches with a verified fix

Medium technical severity with no CISA KEV confirmation; remediate through the normal risk-based patch cycle unless local exposure raises the priority. Verified remediation exists for at least one product or source, but 15 structured product or package states remain unresolved. Apply remediation only to the exact product branch confirmed by its source.

Fix availability varies by product
R
Operational reassessment

Published severity in operational context

Open reassessment dashboard →
Published severityMediumOperational priority:Low, lowered one band.downgradedsince 12 May 2026

Evidence used

  • No CISA KEV confirmation is currently recorded.
  • Exploitation requires an existing local or physical foothold with privileges.
  • EPSS is 0.10% for the current model date.

Compensating controls

  • Apply the linked authoritative mitigation while planning the permanent fix.
  • Restrict local access and enforce least privilege on affected hosts.
  • Monitor vendor guidance and exploitation sources for a material change.

Verification

  1. Confirm that the asset runs Unknown Intel(R) Processors and falls inside the recorded affected range.
  2. Recheck the vendor advisory before scheduling a change because no verified fixed version is currently retained.
  3. Validate exposure, authentication requirements and compensating controls in the actual environment.
  4. Reopen this reassessment when CVSS, KEV, EPSS, exploit evidence or remediation changes.
Mitigation target: No default targetRemediation target: Normal maintenance

This automated reassessment organises public evidence. It does not know asset exposure, business impact or control effectiveness and does not replace CVSS or a human risk decision.

Cross-source reconciliation

Remediation availability differs by product scope

Verified remediation exists for at least one product or source, but 15 structured product or package states remain unresolved. Apply remediation only to the exact product branch confirmed by its source.

Distribution package intelligence

Release-specific package status

Alpine, Debian, ubuntu findings are scoped to the named distribution, release and source package. An absent finding does not mean a package is unaffected.

8 package states
Package result overrides the generic status

BlackTree has verified remediation for at least one product or source, but the relevant distribution still reports no fixed package for 4 affected package states shown here. Treat those rows as affected with no fix until that distribution publishes a fixed version.

Repository candidate not checked

A published vendor fix does not prove that a matching update is enabled and installable on a particular asset. Confirm the local package candidate before scheduling remediation.

Distribution releaseSource packageVendor stateFixed versionEvidence
Alpine v3.23v3.23 · mainintel-ucodeVendor fix publishedAlpine records a security fix at this version. An absent entry does not mean the package is unaffected.20260512-r0Alpine Security Database ↗Source updated 3 Oct 2026
Alpine v3.22v3.22 · mainintel-ucodeVendor fix publishedAlpine records a security fix at this version. An absent entry does not mean the package is unaffected.20260512-r0Alpine Security Database ↗Source updated 3 Oct 2026
Alpine v3.21v3.21 · mainintel-ucodeVendor fix publishedAlpine records a security fix at this version. An absent entry does not mean the package is unaffected.20260512-r0Alpine Security Database ↗Source updated 3 Oct 2026
Debian trixietrixie · sourceintel-microcodeAffected, no fix publishedDebian currently tracks this release as open.Not published in this feedDebian Security Tracker ↗Source updated 6 Oct 2026
Debian bookwormbookworm · sourceintel-microcodeAffected, no fix publishedDebian currently tracks this release as open.Not published in this feedDebian Security Tracker ↗Source updated 6 Oct 2026
Debian forkyforky · sourceintel-microcodeAffected, no fix publishedDebian currently tracks this release as open.Not published in this feedDebian Security Tracker ↗Source updated 6 Oct 2026
Debian sidsid · sourceintel-microcodeAffected, no fix publishedDebian currently tracks this release as open.Not published in this feedDebian Security Tracker ↗Source updated 6 Oct 2026
Ubuntu 24.04 LTSnoble · standard archiveintel-microcodeUnder evaluationCanonical reports that the package might be affected and still needs evaluation or fixing.Not published in this feedCanonical Ubuntu Security ↗Source updated 5 Oct 2026
Direct vendor intelligence

Authoritative vendor CSAF and VEX advisories

Structured product status and remediation from the issuing vendor. Product-state explanations are always visible; large lists can be searched or downloaded.

1 current
CVE-2025-35979 · CSAF 2.0 · revision 3 · finalRed Hat Product Securitykernel: Kernel: Information disclosure via shared microarchitectural predictor state in Intel(R) Processors
11 known affected

The vendor explicitly identifies these products as affected by this CVE.

  • microcode_ctl.src as a component of Red Hat Enterprise Linux 10
  • microcode_ctl as a component of Red Hat Enterprise Linux 6
  • microcode_ctl.src as a component of Red Hat Enterprise Linux 6
  • microcode_ctl as a component of Red Hat Enterprise Linux 7
  • microcode_ctl.src as a component of Red Hat Enterprise Linux 7
  • microcode_ctl as a component of Red Hat Enterprise Linux 8
  • microcode_ctl.src as a component of Red Hat Enterprise Linux 8
  • microcode_ctl as a component of Red Hat Enterprise Linux 9
  • microcode_ctl.src as a component of Red Hat Enterprise Linux 9
  • openshift/ose-rhel-coreos-8 as a component of Red Hat OpenShift Container Platform 4
  • openshift/ose-rhel-coreos-9 as a component of Red Hat OpenShift Container Platform 4
Summary
A flaw was found in the kernel. This vulnerability, affecting some Intel(R) Processors, involves shared microarchitectural predictor state that influences transient execution within VMX non-root (guest) operation. An unprivileged software adversary with an authenticated user can exploit this locally to disclose sensitive information. This high-complexity attack requires no user interaction and can lead to significant data exposure.
Remediation
Mitigation for this issue is either not available or the currently available options do not meet the Red Hat Product Security criteria comprising ease of use and deployment, applicability to widespread installation base, or stability.
Optional official sources

National CERT insights
?CERT means Computer Emergency Response Team; CSIRT is the closely related term Computer Security Incident Response Team.

Choose official national sources for this report. Each advisory shows its original language. Your selection is remembered on this device and included in shared links.

Official European source

ENISA European Vulnerability Database

Official EUVD identifiers, advisory evidence and known-exploited context. Missing fields are not treated as evidence of low risk.

1 current
ENISA EUVD identifier

EUVD-2025-209791

No EUVD known-exploited evidence

ENISA has published the identifier mapping but no EUVD description has been stored yet.

EUVD state
Present in the current official mapping
Known exploitation
Not present in the current ENISA EUVD known-exploited dataset. This is not proof of no exploitation.
ENISA score
Not supplied in the stored EUVD record
Advisory evidence
No linked advisory details stored yet
Recommended actionPatch only the product branches with a verified fix

Medium technical severity with no CISA KEV confirmation; remediate through the normal risk-based patch cycle unless local exposure raises the priority. Verified remediation exists for at least one product or source, but 15 structured product or package states remain unresolved. Apply remediation only to the exact product branch confirmed by its source.

Fix availability varies by product
01

What, why and how

Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R) Processors within VMX non-root (guest) operation may allow an information disclosure. Unprivileged software adversary with an authenticated user combined with a high complexity attack may enable data exposure. This result may potentially occur via local access when attack requirements are present without special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (high), integrity (none) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (high), integrity (none) and availability (none) impacts.

What

Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R) Processors within VMX non-root (guest) operation may allow an information disclosure. Unprivileged software adversary with an authenticated user combined with a high complexity attack may enable data exposure. This result may potentially occur via local access when attack requirements are present without special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (high), integrity (none) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (high), integrity (none) and availability (none) impacts.

Why

Shared microarchitectural predictor state may allow code to influence transient execution across a hardware boundary, potentially exposing data that is accessible beyond the boundary over a covert channel.

How

An attacker operating through local access may attempt exploitation with low privileges. If successful, the issue may obtain information outside the intended access boundary.

What

Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R) Processors within VMX non-root (guest) operation may allow an information disclosure. Unprivileged software adversary with an authenticated user combined with a high complexity attack may enable data exposure. This result may potentially occur via local access when attack requirements are present without special internal knowledge and requires no user interaction. The potential vulnerability may impact the confidentiality (high), integrity (none) and availability (none) of the vulnerable system, resulting in subsequent system confidentiality (high), integrity (none) and availability (none) impacts.

Why

Shared microarchitectural predictor state may allow code to influence transient execution across a hardware boundary, potentially exposing data that is accessible beyond the boundary over a covert channel.

How

An attacker operating through local access may attempt exploitation with low privileges. If successful, the issue may obtain information outside the intended access boundary.

02

Exploit reality and attack path

CVSS severity, EPSS forecast probability, public exploit material and CISA-confirmed exploitation are separate signals.

Observed exploitation
?Confirmed exploitation and public exploit material are separate signals. Attacks can occur without public proof-of-concept or exploit code.
No confirmed evidence

No CISA KEV match was present at the last successful refresh. This means no confirmation from that source, not proof of no exploitation.

Public PoC / exploit material
?Confirmed exploitation and public exploit material are separate signals. Attacks can occur without public proof-of-concept or exploit code.
None recorded

No exploit-tagged reference or CISA SSVC proof-of-concept state is currently recorded. Research may still exist outside the structured feeds.

Likely attack path
local access → Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution → obtain information outside the intended access boundary
Attack surface
Local
Privileges required
Low: a basic authenticated account is required
User interaction
None
Attack complexity
High: exploitation depends on specific conditions
Security boundary
Not a CVSS 4.0 base metric
Weakness
?CWE means Common Weakness Enumeration: a standard category for the underlying weakness.
CWE-1423 ↗

CWE-1423: Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution. Shared microarchitectural predictor state may allow code to influence transient execution across a hardware boundary, potentially exposing data that is accessible beyond the boundary over a covert channel.

CVSS vector
?CVSS means Common Vulnerability Scoring System. The vector records the metric values used to calculate technical severity.
CVSS:4.0/AV:L/AC:H/AT:P/PR:L/UI:N/VC:H/VI:N/VA:N/SC:H/SI:N/SA:N

Common Vulnerability Scoring System 4.0: the compact vector below is decoded into plain language.

AVLocalAttack vector: The attacker needs local access to the vulnerable system.ACHighAttack complexity: Successful exploitation depends on specific conditions outside the attacker's direct control.ATPresentAttack requirements: A particular deployment or execution condition must be present.PRLowPrivileges required: The attacker needs basic user-level privileges.UINoneUser interaction: No action by another user is required.VCHighVulnerable-system confidentiality: A successful attack can cause a major loss.VINoneVulnerable-system integrity: No direct loss is represented by this metric.VANoneVulnerable-system availability: No direct loss is represented by this metric.SCHighSubsequent-system confidentiality: A successful attack can cause a major loss.SINoneSubsequent-system integrity: No direct loss is represented by this metric.SANoneSubsequent-system availability: No direct loss is represented by this metric.
Post-exploitation / living off the land
The issue can support a local privilege or sandbox boundary transition; normal system utilities may then be available in the gained context.
CWE-1423
A

Official authority intelligence

Only matched European and national findings are included. Language selectors and unavailable sources are omitted.

BSI · German · WID-SEC-2026-1480Intel Prozessor: Mehrere Schwachstellen

Ein lokaler Angreifer kann mehrere Schwachstellen in Intel Prozessor ausnutzen, um erweiterte Privilegien zu erlangen oder vertrauliche Informationen offenzulegen.

Official advisory ↗
03

Patch and workaround

Operational remediation based on structured source evidence.

Status
?Patch availability is based on structured fixed-version fields and authoritative update references. If no fix is verified, check the vendor advisory before making a change.
Fix availability varies by product
Affected
Fixed
No fixed version is explicitly recorded in the structured CVE data.
Action
Use the product-specific evidence above. Patch only products with a verified fixed release, and keep every affected or under-investigation state without a matching fix in the remediation queue.
Workaround
Mitigation for this issue is either not available or the currently available options do not meet the Red Hat Product Security criteria comprising ease of use and deployment, applicability to widespread installation base, or stability.
04

Evidence and provenance

Published 12 May 2026 · Last source change 12 May 2026, 17:06 UTC · CWE-1423 · Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution

CVE recordCVE.org · 5.2
CVSS sourceCNA
EPSS source
?The date BlackTree first stored a score for this CVE from the daily FIRST EPSS feed.
FIRST · tracked since 2026-08-14
European sourceENISA EUVD · EUVD-2025-209791
Product sourceVendor CSAF · Red Hat Product Security
Remediation sourceVendor CSAF · Red Hat Product Security
CWE sourceCNA
NVD statusNVD awaiting enrichment

Missing structured fields: affected product. Missing data is not evidence of low risk; review the primary advisory.

Material change intelligence

What changed after publication

View recent updates ↗
  1. Affected versionsThe structured affected or fixed version information changed.
    Before
    microcode_ctl.src as a component of Red Hat Enterprise Linux 10; microcode_ctl as a component of Red Hat Enterprise Linux 6; microcode_ctl.src as a component of Red Hat Enterprise Linux 6; microcode_ctl as a component of Red Hat Enterprise Linux 7; microcode_ctl.src as a component of Red Hat Enterprise Linux 7; microcode_ctl as a component of Red Hat Enterprise Linux 8; microcode_ctl.src as a component of Red Hat Enterprise Linux 8; microcode_ctl as a component of Red Hat Enterprise Linux 9; microcode_ctl.src as a component of Red Hat Enterprise Linux 9; openshift/ose-rhel-coreos-9 as a component of Red Hat OpenShift Container Platform 4
    After
    microcode_ctl.src as a component of Red Hat Enterprise Linux 10; microcode_ctl as a component of Red Hat Enterprise Linux 6; microcode_ctl.src as a component of Red Hat Enterprise Linux 6; microcode_ctl as a component of Red Hat Enterprise Linux 7; microcode_ctl.src as a component of Red Hat Enterprise Linux 7; microcode_ctl as a component of Red Hat Enterprise Linux 8; microcode_ctl.src as a component of Red Hat Enterprise Linux 8; microcode_ctl as a component of Red Hat Enterprise Linux 9; microcode_ctl.src as a component of Red Hat Enterprise Linux 9; openshift/ose-rhel-coreos-8 as a component of Red Hat OpenShift Container Platform 4; openshift/ose-rhel-coreos-9 as a component of Red Hat OpenShift Container Platform 4
    Red Hat Product Security ↗
Material fields only · duplicate refreshes suppressed · history retained for the configured operational retention period
CVE published
ENISA EUVD · EUVD-2025-209791↗Vendor CSAF · Red Hat Product Security↗CVE authority or vendor reference↗Official CVE record (CNA and ADP data)↗NVD record↗
Technical terms and abbreviations used in this report
CVE
Common Vulnerabilities and Exposures: the public identifier for one disclosed vulnerability.
CVSS
Common Vulnerability Scoring System: a technical severity framework; it is not patching priority by itself.
EPSS
Exploit Prediction Scoring System: FIRST's estimate of the probability that exploitation activity will be observed in the next 30 days; it is a forecast, not confirmation.
CWE
Common Weakness Enumeration: the standard category describing the underlying software or hardware weakness.
CNA
CVE Numbering Authority: an organisation authorised to assign and publish CVE records.
CISA ADP
Cybersecurity and Infrastructure Security Agency Authorized Data Publisher: structured enrichment added to a CVE record.
NVD
National Vulnerability Database: NIST's enrichment service for CVE records.
CERT / CSIRT
A computer security incident response team that publishes warnings or coordinates incident response.
PoC
Proof of concept: public material that demonstrates or helps reproduce exploitation.
CSAF
Common Security Advisory Framework: a machine-readable format for security advisories.
LoTL
Living off the land: abuse of legitimate tools or system functions during an attack.
Free version - for non-commercial use only.CVE-2025-35979 · cve.blacktree.nl