Evidence used
- No CISA KEV confirmation is currently recorded.
- Exploitation requires an existing local or physical foothold with privileges.
- EPSS is 0.19% for the current model date.
BlackTreeCVE IntelligenceFull vulnerability report · 2025
CVE-2025-20623High confidence
n/a Intel(R) Core™ processors (10th Generation) — Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution
Unknown · Intel(R) Core™ processors (10th Generation)
5.7MediumCVSS 4.0
Scheduled
Fix not verifiedMedium technical severity with no CISA KEV confirmation; remediate through the normal risk-based patch cycle unless local exposure raises the priority.
R
Open reassessment dashboard →Operational reassessment
Published severity in operational context
Published severityMedium→Operational priority:Low, lowered one band.downgradedsince 3 Nov 2025
Compensating controls
- Restrict local access and enforce least privilege on affected hosts.
- Monitor vendor guidance and exploitation sources for a material change.
Verification
- Confirm that the asset runs Unknown Intel(R) Core™ processors (10th Generation) and falls inside the recorded affected range.
- Recheck the vendor advisory before scheduling a change because no verified fixed version is currently retained.
- Validate exposure, authentication requirements and compensating controls in the actual environment.
- Reopen this reassessment when CVSS, KEV, EPSS, exploit evidence or remediation changes.
Distribution package intelligence
8 package statesRelease-specific package status
Alpine, Debian, ubuntu findings are scoped to the named distribution, release and source package. An absent finding does not mean a package is unaffected.
Repository candidate not checked
A published vendor fix does not prove that a matching update is enabled and installable on a particular asset. Confirm the local package candidate before scheduling remediation.
| Distribution release | Source package | Vendor state | Fixed version | Evidence |
|---|---|---|---|---|
| Alpine v3.23v3.23 · main | intel-ucode | Vendor fix publishedAlpine records a security fix at this version. An absent entry does not mean the package is unaffected. | 20250512-r0 | Alpine Security Database ↗Source updated 3 Oct 2026 |
| Alpine v3.22v3.22 · main | intel-ucode | Vendor fix publishedAlpine records a security fix at this version. An absent entry does not mean the package is unaffected. | 20250512-r0 | Alpine Security Database ↗Source updated 3 Oct 2026 |
| Alpine v3.21v3.21 · main | intel-ucode | Vendor fix publishedAlpine records a security fix at this version. An absent entry does not mean the package is unaffected. | 20250512-r0 | Alpine Security Database ↗Source updated 3 Oct 2026 |
| Debian trixietrixie · source | intel-microcode | Vendor fix publishedDebian records a fixed source-package version for this release. | 3.20250512.1 | Debian Security Tracker ↗Source updated 5 Oct 2026 |
| Debian bookwormbookworm · source | intel-microcode | Vendor fix publishedDebian records a fixed source-package version for this release. | 3.20250512.1~deb12u1 | Debian Security Tracker ↗Source updated 5 Oct 2026 |
| Debian forkyforky · source | intel-microcode | Vendor fix publishedDebian records a fixed source-package version for this release. | 3.20250512.1 | Debian Security Tracker ↗Source updated 5 Oct 2026 |
| Debian sidsid · source | intel-microcode | Vendor fix publishedDebian records a fixed source-package version for this release. | 3.20250512.1 | Debian Security Tracker ↗Source updated 5 Oct 2026 |
| Ubuntu 24.04 LTSnoble · standard archive | intel-microcode | Vendor fix publishedCanonical reports that a fixed source package version has been published. Repository candidate availability is not checked by BlackTree. | 3.20250512.0ubuntu0.24.04.1 | Canonical Ubuntu Security ↗Source updated 5 Oct 2026 |
Medium technical severity with no CISA KEV confirmation; remediate through the normal risk-based patch cycle unless local exposure raises the priority.
Fix not verified01
What, why and how
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R) Core™ processors (10th Generation) may allow an authenticated user to potentially enable information disclosure via local access.
What
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R) Core™ processors (10th Generation) may allow an authenticated user to potentially enable information disclosure via local access.
Why
Shared microarchitectural predictor state may allow code to influence transient execution across a hardware boundary, potentially exposing data that is accessible beyond the boundary over a covert channel.
How
An attacker operating through local access may attempt exploitation with low privileges. If successful, the issue may obtain information outside the intended access boundary.
What
Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel(R) Core™ processors (10th Generation) may allow an authenticated user to potentially enable information disclosure via local access.
Why
Shared microarchitectural predictor state may allow code to influence transient execution across a hardware boundary, potentially exposing data that is accessible beyond the boundary over a covert channel.
How
An attacker operating through local access may attempt exploitation with low privileges. If successful, the issue may obtain information outside the intended access boundary.
02
Exploit reality and attack path
CVSS severity, EPSS forecast probability, public exploit material and CISA-confirmed exploitation are separate signals.
Observed exploitation No confirmed evidence
?
Confirmed exploitation and public exploit material are separate signals. Attacks can occur without public proof-of-concept or exploit code.No CISA KEV match was present at the last successful refresh. This means no confirmation from that source, not proof of no exploitation.
Public PoC / exploit material None recorded
?
Confirmed exploitation and public exploit material are separate signals. Attacks can occur without public proof-of-concept or exploit code.No exploit-tagged reference or CISA SSVC proof-of-concept state is currently recorded. Research may still exist outside the structured feeds.
- Likely attack path
- local access → Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution → obtain information outside the intended access boundary
- Attack surface
- Local
- Privileges required
- Low: a basic authenticated account is required
- User interaction
- None
- Attack complexity
- High: exploitation depends on specific conditions
- Security boundary
- Not a CVSS 4.0 base metric
- Weakness
?
CWE means Common Weakness Enumeration: a standard category for the underlying weakness. - CWE-1423 ↗
CWE-1423: Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution. Shared microarchitectural predictor state may allow code to influence transient execution across a hardware boundary, potentially exposing data that is accessible beyond the boundary over a covert channel.
- CVSS vector
?
CVSS means Common Vulnerability Scoring System. The vector records the metric values used to calculate technical severity. CVSS:4.0/AV:L/AC:H/AT:P/PR:L/UI:N/VC:H/VI:N/VA:N/SC:N/SI:N/SA:NCommon Vulnerability Scoring System 4.0: the compact vector below is decoded into plain language.
AVLocalAttack vector: The attacker needs local access to the vulnerable system.ACHighAttack complexity: Successful exploitation depends on specific conditions outside the attacker's direct control.ATPresentAttack requirements: A particular deployment or execution condition must be present.PRLowPrivileges required: The attacker needs basic user-level privileges.UINoneUser interaction: No action by another user is required.VCHighVulnerable-system confidentiality: A successful attack can cause a major loss.VINoneVulnerable-system integrity: No direct loss is represented by this metric.VANoneVulnerable-system availability: No direct loss is represented by this metric.SCNoneSubsequent-system confidentiality: No direct loss is represented by this metric.SINoneSubsequent-system integrity: No direct loss is represented by this metric.SANoneSubsequent-system availability: No direct loss is represented by this metric.- Post-exploitation / living off the land
- The issue can support a local privilege or sandbox boundary transition; normal system utilities may then be available in the gained context.
03
Patch and workaround
Operational remediation based on structured source evidence.
- Status
?
Patch availability is based on structured fixed-version fields and authoritative update references. If no fix is verified, check the vendor advisory before making a change. - Fix not verified
- Affected
- Intel(R) Core™ processors (10th Generation): See references
- Fixed
- No fixed version is explicitly recorded in the structured CVE data.
- Action
- No verified patch reference is present in the current structured sources. Check the vendor advisory before making a change.
- Workaround
- No verified workaround is recorded. Limit untrusted access and use least privilege until authoritative guidance is available.
04
Evidence and provenance
Published 13 May 2025 · Last source change 3 Nov 2025, 19:35 UTC · CWE-1423 · Exposure of Sensitive Information caused by Shared Microarchitectural Predictor State that Influences Transient Execution
CVE recordCVE.org · 5.2
CVSS sourceCNA
EPSS source FIRST · tracked since 2026-08-14
?
The date BlackTree first stored a score for this CVE from the daily FIRST EPSS feed.European sourceENISA EUVD · EUVD-2025-14553
Product sourceCNA
Remediation sourceCVE/CNA references
CWE sourceCNA
NVD statusNVD not scheduled
Missing structured fields: affected product. Missing data is not evidence of low risk; review the primary advisory.
Material change intelligence
View recent updates ↗What changed after publication
No material field changes have been recorded since change tracking began. Routine source refreshes and cosmetic edits are intentionally excluded.
Technical terms and abbreviations used in this report
- CVE
- Common Vulnerabilities and Exposures: the public identifier for one disclosed vulnerability.
- CVSS
- Common Vulnerability Scoring System: a technical severity framework; it is not patching priority by itself.
- EPSS
- Exploit Prediction Scoring System: FIRST's estimate of the probability that exploitation activity will be observed in the next 30 days; it is a forecast, not confirmation.
- CWE
- Common Weakness Enumeration: the standard category describing the underlying software or hardware weakness.
- CNA
- CVE Numbering Authority: an organisation authorised to assign and publish CVE records.
- CISA ADP
- Cybersecurity and Infrastructure Security Agency Authorized Data Publisher: structured enrichment added to a CVE record.
- NVD
- National Vulnerability Database: NIST's enrichment service for CVE records.
- CERT / CSIRT
- A computer security incident response team that publishes warnings or coordinates incident response.
- PoC
- Proof of concept: public material that demonstrates or helps reproduce exploitation.
- CSAF
- Common Security Advisory Framework: a machine-readable format for security advisories.
- LoTL
- Living off the land: abuse of legitimate tools or system functions during an attack.