Evidence used
- No CISA KEV confirmation is currently recorded.
- Exploitation requires an existing local or physical foothold with privileges.
- EPSS is 0.15% for the current model date.
BlackTreeCVE IntelligenceFull vulnerability report · 2024
CVE-2023-32666High confidence
n/a 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX — On-Chip Debug and Test Interface With Improper Access Control
Unknown · 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX
7.2HighCVSS 3.1
Within 7 days
Fix not verifiedHigh technical severity; prioritise exposed affected systems while verifying vendor guidance.
R
Open reassessment dashboard →Operational reassessment
Published severity in operational context
Published severityHigh→Operational priority:Medium, lowered one band.downgradedsince 13 Feb 2025
Compensating controls
- Restrict local access and enforce least privilege on affected hosts.
- Monitor vendor guidance and exploitation sources for a material change.
Verification
- Confirm that the asset runs Unknown 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX and falls inside the recorded affected range.
- Recheck the vendor advisory before scheduling a change because no verified fixed version is currently retained.
- Validate exposure, authentication requirements and compensating controls in the actual environment.
- Reopen this reassessment when CVSS, KEV, EPSS, exploit evidence or remediation changes.
High technical severity; prioritise exposed affected systems while verifying vendor guidance.
Fix not verified01
What, why and how
On-chip debug and test interface with improper access control in some 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX may allow a privileged user to potentially enable escalation of privilege via local access.
What
On-chip debug and test interface with improper access control in some 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX may allow a privileged user to potentially enable escalation of privilege via local access.
Why
The chip does not implement or does not correctly perform access control to check whether users are authorized to access internal registers and test modes through the physical debug/test interface.
How
An attacker operating through local access may attempt exploitation with elevated privileges. If successful, the issue may cause the confidentiality, integrity or availability impact described by the vendor.
What
On-chip debug and test interface with improper access control in some 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX may allow a privileged user to potentially enable escalation of privilege via local access.
Why
The chip does not implement or does not correctly perform access control to check whether users are authorized to access internal registers and test modes through the physical debug/test interface.
How
An attacker operating through local access may attempt exploitation with elevated privileges. If successful, the issue may cause the confidentiality, integrity or availability impact described by the vendor.
02
Exploit reality and attack path
CVSS severity, EPSS forecast probability, public exploit material and CISA-confirmed exploitation are separate signals.
Observed exploitation No confirmed evidence
?
Confirmed exploitation and public exploit material are separate signals. Attacks can occur without public proof-of-concept or exploit code.No CISA KEV match was present at the last successful refresh. This means no confirmation from that source, not proof of no exploitation.
Public PoC / exploit material None recorded
?
Confirmed exploitation and public exploit material are separate signals. Attacks can occur without public proof-of-concept or exploit code.No exploit-tagged reference or CISA SSVC proof-of-concept state is currently recorded. Research may still exist outside the structured feeds.
- Likely attack path
- local access → On-Chip Debug and Test Interface With Improper Access Control → cause the confidentiality, integrity or availability impact described by the vendor
- Attack surface
- Local
- Privileges required
- High: elevated access is required
- User interaction
- None
- Attack complexity
- High: exploitation depends on specific conditions
- Security boundary
- Changed: exploitation can affect a different security authority
- Weakness
?
CWE means Common Weakness Enumeration: a standard category for the underlying weakness. - CWE-1191 ↗
CWE-1191: On-Chip Debug and Test Interface With Improper Access Control. The chip does not implement or does not correctly perform access control to check whether users are authorized to access internal registers and test modes through the physical debug/test interface.
- CVSS vector
?
CVSS means Common Vulnerability Scoring System. The vector records the metric values used to calculate technical severity. CVSS:3.1/AV:L/AC:H/PR:H/UI:N/S:C/C:H/I:H/A:NCommon Vulnerability Scoring System 3.1: the compact vector below is decoded into plain language.
AVLocalAttack vector: The attacker needs local access to the vulnerable system.ACHighAttack complexity: Successful exploitation depends on specific conditions outside the attacker's direct control.PRHighPrivileges required: The attacker needs elevated or administrative privileges.UINoneUser interaction: No action by another user is required.SChangedScope: The attack can affect a component governed by a different security authority.CHighConfidentiality impact: A successful attack can cause a major loss.IHighIntegrity impact: A successful attack can cause a major loss.ANoneAvailability impact: No direct loss is represented by this metric.- Post-exploitation / living off the land
- The issue can support a local privilege or sandbox boundary transition; normal system utilities may then be available in the gained context.
03
Patch and workaround
Operational remediation based on structured source evidence.
- Status
?
Patch availability is based on structured fixed-version fields and authoritative update references. If no fix is verified, check the vendor advisory before making a change. - Fix not verified
- Affected
- 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX: some 4th Generation Intel(R) Xeon(R) Processors when using Intel(R) SGX or Intel(R) TDX
- Fixed
- No fixed version is explicitly recorded in the structured CVE data.
- Action
- No verified patch reference is present in the current structured sources. Check the vendor advisory before making a change.
- Workaround
- No verified workaround is recorded. Limit untrusted access and use least privilege until authoritative guidance is available.
04
Evidence and provenance
Published 14 Mar 2024 · Last source change 13 Feb 2025, 16:54 UTC · CWE-1191 · On-Chip Debug and Test Interface With Improper Access Control
CVE recordCVE.org · 5.1
CVSS sourceCNA
EPSS source FIRST · tracked since 2026-08-14
?
The date BlackTree first stored a score for this CVE from the daily FIRST EPSS feed.European sourceENISA EUVD · EUVD-2023-36909
Product sourceCNA
Remediation sourceCVE/CNA references
CWE sourceCNA
NVD statusNVD not scheduled
Missing structured fields: affected product. Missing data is not evidence of low risk; review the primary advisory.
Material change intelligence
View recent updates ↗What changed after publication
No material field changes have been recorded since change tracking began. Routine source refreshes and cosmetic edits are intentionally excluded.
Technical terms and abbreviations used in this report
- CVE
- Common Vulnerabilities and Exposures: the public identifier for one disclosed vulnerability.
- CVSS
- Common Vulnerability Scoring System: a technical severity framework; it is not patching priority by itself.
- EPSS
- Exploit Prediction Scoring System: FIRST's estimate of the probability that exploitation activity will be observed in the next 30 days; it is a forecast, not confirmation.
- CWE
- Common Weakness Enumeration: the standard category describing the underlying software or hardware weakness.
- CNA
- CVE Numbering Authority: an organisation authorised to assign and publish CVE records.
- CISA ADP
- Cybersecurity and Infrastructure Security Agency Authorized Data Publisher: structured enrichment added to a CVE record.
- NVD
- National Vulnerability Database: NIST's enrichment service for CVE records.
- CERT / CSIRT
- A computer security incident response team that publishes warnings or coordinates incident response.
- PoC
- Proof of concept: public material that demonstrates or helps reproduce exploitation.
- CSAF
- Common Security Advisory Framework: a machine-readable format for security advisories.
- LoTL
- Living off the land: abuse of legitimate tools or system functions during an attack.